The present invention relates to a printed wiring board for a semiconductor package of a multilayered structure having a power supply layer and the like as internal layers, or to a semiconductor package obtained by packaging a semiconductor chip using the above wiring board.
In some cases, a semiconductor package structure employs a multilayered printed wiring board having a solid power supply layer and ground layer as internal layers in order to improve the electrical characteristics of signals.
FIG. 5 shows the two-dimensional structure of a printed wiring board for a semiconductor package 110 used in a semiconductor package to which the present invention pertains. A portion on which a semiconductor chip is placed is removed as a cavity 143. A ground pattern 112 is formed to surround this cavity 143. A power supply pattern 113 is formed around the ground pattern 112. The ground and power supply patterns 112 and 113 are formed as integral rings, respectively. That portion of each pattern which is subjected to wire bonding is exposed, and the remaining portion is covered with an insulating film of solder resist or the like.
A plurality of signal pins 114 are radially formed around the power supply pattern 113. A ball grid array (to be referred to as a BGA hereinafter) 111 is formed around the signal pins 114 to be spaced apart from a wiring region 154. The BGA 111 serves as a connection means for mounting a semiconductor package on a printed wiring board (not shown).
FIG. 7 is a partial enlarged plan view of a portion near the side surface of the cavity 143 when the printed wiring board for a semiconductor package 110 is mounted on a heat spreader and a semiconductor chip is mounted in the cavity 143. FIG. 6 is a longitudinal sectional view taken along the line Bxe2x80x94B in FIG. 7.
The printed wiring board for a semiconductor package 110 is adhered on a heat spreader 131 made of a conductive material by using an adhesive tape 132 made of an insulating material. A semiconductor chip 141 is bonded in the cavity 143 of the printed wiring board 110 with silver paste 142. The ground pattern 112, power supply pattern 113, and signal pins 114 are formed on the surface of the printed wiring board 110, while a ground layer 121 and power supply layer 122 are formed as internal layers of the printed wiring board 110. The ground pattern and power supply pattern 112 and 113 are connected to the ground and power supply layers 121 and 122 via through holes 123, respectively. The pads of the semiconductor chip 141 are connected to the ground pattern 112, power supply pattern 113, and signal pins 114 of the printed wiring board 110 via bonding wires 151 to 153, respectively.
The above printed wiring board for a semiconductor package, however, suffers the following problems.
The same plating as in the through hole 123 is made on the inner surface of the cavity 143 to form side wall plating 115. This side wall plating 115 serves to connect the ground pattern 112 near the cavity 143 to the ground layer 121 serving as an internal layer. This allows connecting the ground pattern 112 and ground layer 121 by a short wiring length with a large contact area. This improves the electrical characteristics.
The side wall plating 115 must uniformly cover a very large area as the entire inner side wall of the cavity 143 unlike general through hole plating. In addition, the side wall of the cavity 143 has burs upon forming the cavity 143. It is difficult to uniformly plate an uneven end face, resulting in a low yield and high cost.
Although the ground pattern 112 can be connected to the ground layer 121 via the side wall plating 115, the power supply pattern 113 and power supply layer 122, which are formed around the ground pattern 112, must be connected via the through hole 123. This increases the wiring length, and the number of through holes is limited. This degrades the electrical characteristics to interfere with transfer of a high-speed signal.
As shown in FIG. 7, to bond the power supply pattern 113 with wires 152, no through hole 123 is formed immediately under the power supply pattern 113. The through holes 123 must be formed at positions shifted outside the power supply pattern 113. The signal pins 114 located around the power supply pattern 113 are away from the semiconductor chip 141. This increases the length of the bonding wires 153 for connecting the signal pins 114 to the semiconductor chip 141 and degrades the electrical characteristics.
It is therefore an object of the present invention to provide a semiconductor package and printed wiring board for a semiconductor package, which can improve the electrical characteristics and reduce the cost.
A semiconductor package according to the present invention comprises a flat mount board, a printed wiring board mounted on the mount board, and a semiconductor chip mounted in a cavity of the printed wiring board on the mount board and electrically connected to the printed wiring board, the printed wiring board comprising a wiring pattern formed on a surface of the printed wiring board, at least one internal layer, and a bump for electrically connecting the wiring pattern and internal layer.
A printed wiring board for a semiconductor package according to the present invention which is electrically connected to a semiconductor chip and has a cavity in which the semiconductor chip is mounted, comprises a wiring pattern formed on a surface of the printed wiring board, at least one internal layer, and a bump for electrically connecting the wiring pattern and internal layer.
The wiring pattern may comprise a first wiring pattern arranged to surround the cavity, a second wiring pattern located around the first wiring pattern so as to surround the cavity, and a plurality of signal pins located around the second wiring pattern so as to surround the cavity. The internal layer may include a first plane internal layer connected to the first wiring layer via the bump and a second plane internal layer connected to the second wiring pattern via the bump.
The first wiring pattern, second wiring pattern, and signal pins are electrically connected to the corresponding pads of the semiconductor chip via bonding wires, respectively.
Each of the first and second wiring patterns is formed into a ring like shape and has a bonding wire connection portion whose surface is exposed and a remaining portion covered with an insulating film of solder resist, and the signal pins are radially formed.
A ball grid array may be located around the signal pins.
The printed wiring board may use a board having a first copper foil for forming a wiring pattern on a first surface, a first bump formed on one of surfaces of the first copper foil, a second copper foil for forming a wiring pattern on a second surface, a first prepreg formed between one surface of the first copper foil and one surface of the second copper foil and electrically connected to the first and second copper foils by extending the first bump through the first prepreg, a third copper foil for forming a wiring pattern on a third surface, a second bump formed on one of surfaces of the third copper foil, a second prepreg formed between the other surface of the first copper foil and one surface of the third copper foil and electrically connected to the first and third copper foils by extending the second bump through the second prepreg, a fourth copper foil for forming a wiring pattern on a fourth surface, a third bump formed on one of surfaces of the fourth copper foil, and a third prepreg formed between the other surface of the second copper foil and one surface of the fourth copper foil and electrically connected to the second and fourth copper foils by extending the third bump through the third prepreg.
In this case, the wiring pattern of the third surface may include the first wiring pattern, second wiring pattern, and signal pins. The wiring pattern of the first surface may include the first or second internal layer, and the wiring pattern of the second surface may include the second or first internal layer.
According to the semiconductor package and printed wiring board for a semiconductor package according to the present invention, the wiring pattern formed on the surface is connected to the internal layer via the bump. The inner side surface of the cavity need not be plated, which increases the yield and reduces the cost.
To connect the wiring pattern and internal layer via the trough hole, the through hole must be formed beyond the wiring pattern formation region to increase the distance between the semiconductor chip and the signal pins located farthest from the cavity. However, the bump can be located immediately under the wiring pattern to shorten the distance between the signal pin and semiconductor chip, thereby improving the electrical characteristics.